A FAST Hardware Decoder Optimized for Template Features to Obtain Order Book Data in Low Latency
نویسندگان
چکیده
High-Frequency Trading (HFT) systems require high computational performance for real-time trading and data analysis. FAST protocol, an extension of FIX is one the main communication pattern adopted by these systems. This work presents open source hardware component, implemented in Field-Programmable Gate Array (FPGA), to decode market messages produce necessary commands construct order books low latency Brasil Bolsa Balcão B3 stock exchange. The proposed component optimized a template able at average 0.72us throughput 1.4M per second. results are from logs real with size 85 bytes each.
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ژورنال
عنوان ژورنال: Journal of Signal Processing Systems
سال: 2023
ISSN: ['1939-8018', '1939-8115']
DOI: https://doi.org/10.1007/s11265-023-01850-2